Broadcom announced sampling of its 5nm ASIC device for data center and cloud infrastructure. Built on TSMC’s N5 process and measuring 625 mm, this device incorporates PCIe Gen5 protocol, 112-Gbps SerDes, HBM2e memory operating at 3.6 Gbps, and 3.6-Tbps Die2Die PHY IP utilizing TSMC CoWoS interposer technology.
In addition, Broadcom has multiple ASIC devices in development targeting artificial intelligence (AI), high performance computing (HPC) and 5G wireless infrastructure applications.
Benefits of 5nm ASIC Platform vs. Previous Generation
- 2x increase in on-die computation for training and inference applications
- 2x to 4x increase in memory bandwidth with HBM2e and HBM3 PHY
- 2x higher bandwidth serial links with 112-Gbps SerDes
- Up to 30% reduction in power per given work function
- System size and cost reduction with advanced packaging solutions
“This first-to-market 5nm ASIC extends Broadcom’s embedded SoC leadership and paves the way for new innovations across AI, HPC, 5G and hyperscale infrastructure applications,” said Frank Ostojic, senior vice president and general manager of the ASIC Product Division at Broadcom. “Our innovative IP, proven design methodology and partnership with TSMC continue to provide leadership solutions with power, performance and time to market advantage for our customers.”
